5 days old

SoC Physical Design Verification Engineer

Austin, TX
  • Job Code
    200105643
Summary

Summary

Posted: Sep 27, 2019

Role Number: 200105643

At Apple, we work every single day to craft products that enrich people's lives. Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices.

In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC

Key Qualifications

  • You have 5-10 years of physical design experience, with emphasis on physical verification
  • Strong knowledge of physical verification flows and methodology
  • Knowledge of all aspects of ASIC physical design
  • Scripting skills to debug flow related issues and make enhancements as appropriate
  • Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
  • Real chip tapeout experience with a track record of successful signoff
  • Layout design background and experience a plus

Description

As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. You'll collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on padring, bump, RDL design, and working with the package and floorplan teams

Education & Experience

You have a BSEE or MSEE

Additional Requirements

Posted: 2019-11-29 Expires: 2019-12-28

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SoC Physical Design Verification Engineer

Apple, Inc.
Austin, TX

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