14 days old

SoC Physical Design Verification Engineer

Cupertino, CA
  • Job Code
    200037112

Summary

In this highly visible role, you will be responsible for physical verification of an SOC

Key Qualifications

  • The ideal candidate will have 5-10 years of physical design experience, with emphasis on physical verification
  • Strong knowledge of physical verification flows and methodology
  • Knowledge of all aspects of ASIC physical design
  • Scripting skills to debug flow related issues and make enhancements as appropriate
  • Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
  • Real chip tapeout experience with a track record of successful signoff
  • Layout design background and experience a plus

Description

As a member of the physical design team, you would be responsible for:
- Performing various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level
• Interfacing with the CAD/Technology teams for flow bring up and validation
• Working with the Implementation team during the entire chip design cycle to drive signoff closure for tapeout
• Managing schedules and supporting cross-functional engineering effort
- Work on padring, bump, RDL design interfacing with the package and floorplan teams

Education & Experience

BSEE or MSEE

Posted: 2019-10-08 Expires: 2019-11-06

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

SoC Physical Design Verification Engineer

Apple, Inc.
Cupertino, CA

Join us to start saving your Favorite Jobs!

Sign In Create Account
Powered ByCareerCast