As an integral part of Intel's new IDM2.0 strategy, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally.

The Team:
Our design team is part of the Foundry Technology, Engineering, and Customer-Engagement Team within IFS. We are a small, tightly knit group of mixed signal analog, logic, architecture and mask designers located in Folsom California who are dedicated to helping Intel achieve its IDM2.0 goals by enabling world-class foundational and custom IP development and test chips, end-to-end circuit design, and power, performance, area analysis.

The Role:
We are looking for the right person to take the role of SOC Power Lead for Test Chip SoCs. The Lead will seize the opportunity to work with multiple disciplines in order to provide efficient and predictable power model, coordinate, guide and review deliveries from all aspects of ASIC development; Power architecture implementation, Power efficient design, static tools and dynamic simulations through RTL design and netlist. You will be a part of the team providing the full power roll up and prediction. From post-si perspective, the team will coordinate Electrical validation results from system validation and manufacturing process.In this role, you will oversee the different power activities across the different disciplines - starting from uArc definitions, through pre-silicon estimations, power delivery and system-level power structuring, and ending with post-silicon correlation measurements. You will be required to direct and guide pre-silicon engineers utilizing industry standard tools, like PowerArtist and Primetime-PX, for extracting power estimations, and roll-up power consumption model for different use cases. Responsible for working closely with the design team for power delivery requirements across all corners and sign-off the design for Tape-out.

Responsibilities:

Expectations include developing and defining methodologies to ensure the highest possible Silicon quality, overseeing the development of a system of timing indicators that enables the physical team to operate efficiently and ensuring high-quality power models. This role requires strong partnership between the overall design leads, physical design manager, timing team manager, layout integration lead, partition leads and other technical leads to drive execution.

The building blocks will include digital, analog, mixed signal, IO, memory sub blocks and DFT. This will include working with external customers and internal teams for developing requirements for Test Chip Integration and developing strategies for testing including post silicon.

Qualifications

Minimum:

• BS in Electrical or Computer Engineering with 6+ years of experience OR,

• MS in Electrical or Computer Engineering with 4+ years of experience in SoC power design and methodologies experience, Synthesis, SoC Design, Analog/Logic design and/or physical design experience

Experience should be in any combination of the following:

• Experience communicating and working in a multi-Geo multi-cultural environment.

• Expertise and in-depth knowledge of industry standard EDA tools. Power estimation tools experience such as Power Artist or PTPX - Advantage

• Build and maintain a power model using: architectural, design, and process specifications; historical power data; and current generation power estimates

• Define segment-specific workloads for power and thermal specifications

• Influence product definition starting from Pathfinding and Technology Readiness. Wide system view (Arch to MFG)

• Set workload-based power targets for IPs and SoCs that support the market requirements and drive teams to meet these goals

• Deliver power data to partners to enable power delivery design, thermal modeling, and performance optimization

• Audit power estimate quality from IP and SoC teams

• Drive improvements to IP and SOC PnP methodology

• Collaborate worldwide with DCD PnP and cross-functional partner teams including SOC and IP Design, Architecture, Performance, Power Management, Power Delivery, Marketing, Planning, and Process

• Package design and board design understanding

• Proficiency in scripting languages, such as, Python, Perl, and Tcl.

• Knowledge of circuits, SPICE simulations,

• Capable of analyzing and converging process variation, and electrical/manufacturing rules and the modelling of these effects in deep-sub micron processes required.

As an integral part of Intel's new IDM2.0 strategy, we establish Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to Intel's CEO. IFS will be a world-class foundry business and a major US and European-based capacity provider to serve customers globally. We differentiate IFS with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, plus a world-class IP portfolio including x86 cores, graphics, media, display, AI, interconnect, fabric, and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions using industry-standard design packages. Intel dedicates IFS to the success of its customers with entire Profit and Loss responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement, and capacity commitments. IFS is already engaged with customers today, starting with our existing foundry offerings. We are expanding imminently to include our most advanced technologies optimized for cutting-edge performance, making them ideal for high-performance applications.

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Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.