Join the XSD department under XEG Division to design a new architecture of cloud computing server chip. The exciting and challenging role would in the CPUTILE STRUCTURAL DESIGN TEAM. On this project, the CPUTILE is a ground-up design in both RTL and physical design.

Qualifications

In this role, responsibilities include (but not limited to):

• Collaborate with Logic Designers to investigate and evaluate functional features and unique structural design requirements.

• Collaborate with CPUTILE/SOC physical design integration teams to solve design issues affecting partition structural designs.

• Implement physical design with advanced area, power, and timing convergence techniques and considerations.

• Develop custom solutions for unique design issues and challenges.

• Provide technical leadership to the team through technical prowess and innovate problem solving.

• Capable of independently driving technical taskforces when critical issues arisen.

Minimum Qualifications:

• BS with 12+ years of experiences, or MS with 10+ years of experiences degree in Electrical Engineering, or computer Engineering or any similar STEM field.

• Experience in VLSI Design

Preferred Qualifications:

• Gone through full physical design cycle, from arch/feature eval related to physical design, through design execution, and design verification and closure.

• Familiar with Synopsys/Cadence EDA tool sets, such as Fusion Compiler, ICC, PT, PTPX, LEC.

• Familiar with highly structured design requiring custom solutions such as preroutes, preplacement.

• Solid scripting and automation skills.

• Capable and comfortable with diverging from default project methodologies and flows when necessary.

• Familiar with Cheetah2 physical design environment.

The ideal candidate to exhibit the following behavioral traits:

• Solid leadership and mentorship skills.

• Take initiative to tackle challenging problems.

• Problem-solving skills.

• Willing to multitask.

• Solid written and verbal communication skills.

• Willing to work in a dynamic and team-oriented environment.

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.