26 days old

SOC Senior Physical Integration Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0204480
  • Jobs Rated
    19th
Job Description

Join the XSD department under XEG Division to design a new architecture of cloud computing server chip. The exciting and challenging role would in the CPUTILE PHYSICAL DESIGN INTEGRATION TEAM. On this project, the CPUTILE is a ground design in both RTL and physical design.


Qualifications

In this role, responsibilities include (but not limited to):

  • Collaborate with Logic Designers to investigate and evaluate functional features and unique structural design requirements

  • Collaborate with physical partitions and SOC physical design integration teams to solve design issues affecting partition structural designs

  • Implement physical design with advanced area, power, and timing convergence techniques and considerations

  • Develop custom solutions for unique design issues and challenges

  • Provide technical leadership to the team through technical prowess and innovate problem solving

  • Capable of independently driving technical taskforces when critical issues arisen

Minimum Qualifications:

BS with 6+ years of experiences, or MS with 4+ years of experience in EE or Computer engineering.

Experience in Computer Architecture and VLS Design

Preferred Qualifications: (highly desirable):

Completed full physical design cycle, from arch/feature eval related to physical design, through design execution, and to design verification and closure

Familiar with floorplanning, timing constraint budgeting, and multiple voltage domains handling.

Familiar physical integration tools/flows, such as Fusion Design Planning and/or parade, timing rollups, physical assembly

Familiar with Synopsys/Cadence EDA tool sets, such as Fusion Compiler, ICC, PT, PTPX, LEC

Familiar with highly structured design requiring custom solutions such as preroutes, preplacement

Scripting and automation skills

Willing and comfortable with diverging from default project methodologies and flows when necessary

Familiar with Cheetah2 physical design environment

The ideal candidate should exhibit the following behavioral traits:

Leadership and mentorship skills

Take initiative to tackle challenging problems

Problem-solving skills

Willing to multitask

Written and verbal communication skills

Willing to work in a dynamic and team-oriented environment

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Other Locations

US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Jobs Rated Reports for Physicist

Posted: 2022-04-19 Expires: 2022-05-20

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SOC Senior Physical Integration Engineer

Intel
Santa Clara, CA 95050

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Physicist
19th2019 - Physicist
Overall Rating: 19/199
Median Salary: $117,220

Work Environment
Very Good
44/220
Stress
Low
78/220
Growth
Good
60/220
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