5 days old

SOC Timing Lead

Intel
Folsom, CA 95630
  • Job Code
    JR0212811
Job Description

As an integral part of Intel's new IDM2.0 strategy, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally.

The Group:

Our design team is part of the Foundry Technology, Engineering, and Customer-Engagement Team within IFS. We are a small, tightly knit group of mixed signal analog, logic, architecture and mask designers located in Folsom California who are dedicated to helping Intel achieve its IDM2.0 goals by enabling world-class foundational and custom IP development and test chips, end-to-end circuit design, and power, performance, area analysis.

The Person:

We are looking for the right person to take the role of SOC Design Timing Lead for Test Chip SoCs. The SOC Design Timing Team Lead will seize the opportunity in a fast-paced dynamic environment where to lead a high performance design team towards convergence of timing across the entire Test Chip SoC. Responsible for performing sub Full chip level and full chip level hierarchical timing analysis and convergence for complex multi-million gates SOC. Responsible for generating and verifying sub full chip level and full chip level implementation/Sign-off timing constraints for functional modes and other modes like DFT. Responsible for working closely with the clocking team to generate clock balancing guidelines and timing fixes considering all modes all corners and sign-off the design for Tape-out.

Responsibilities:

Expectations include developing and defining methodologies to ensure the highest possible Silicon quality, overseeing the development of a system of timing indicators that enables the physical team to operate efficiently and ensuring high-quality timing models. Expert level knowledge of Primetime and associated timing model build flows is required. The person should have understanding on STA flow development, various report generation and automation on it. This role requires strong partnership between the overall physical design manager, timing team manager, layout integration lead, partition leads and other technical leads to drive execution.

The building blocks will include digital, analog, mixed signal, IO, memory sub blocks and DFT. This will include working with external customers and internal teams for developing requirements for Test Chip Integration and developing strategies for testing including post silicon.


Qualifications

Minimum:

  • BS in Electrical or Computer Engineering with 6+ years of experience OR,

  • MS in Electrical or Computer Engineering with 4+ years of experience in Synthesis, Timing methodologies and flow development.

Experience should be in any combination of the following:

  • Expertise and in-depth knowledge of industry standard EDA tools Prime time, Fusion Compiler, ICC as well as proficiency in scripting languages, such as, Python, Perl, and Tcl.

  • Knowledge of circuits, SPICE simulations, and/or transistor level STA.

  • Demonstrate a deep understanding of Static Timing Analysis, timing constraints generation and management, and timing convergence. You are capable of analyzing and converging cross-talk delay, noise glitch, process variation, and electrical/manufacturing rules and the modelling of these effects in deep-sub micron processes required.

  • Experience in generating, handling and validating timing and SI models to reduce the memory footprint and Sign-off run times and simultaneously ensuring required accuracy at various stages of design cycle

  • Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, and implementing them through ECOs.

  • Hands on experience with developing full chip timing Verification environments

  • Experience in 7 nm, 10 nm and 14nm Implementation flows

Inside this Business Group

As an integral part of Intel's new IDM2.0 strategy, we establish Intel Foundry Services (IFS), a fully vertical, standalone foundry business, reporting directly to Intel's CEO. IFS will be a world-class foundry business and a major US and European-based capacity provider to serve customers globally. We differentiate IFS with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, plus a world-class IP portfolio including x86 cores, graphics, media, display, AI, interconnect, fabric, and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions using industry-standard design packages. Intel dedicates IFS to the success of its customers with entire Profit and Loss responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement, and capacity commitments. IFS is already engaged with customers today, starting with our existing foundry offerings. We are expanding imminently to include our most advanced technologies optimized for cutting-edge performance, making them ideal for high-performance applications.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role is available as fully home-based and generally would require you to attend Intel sites only occasionally based on business need.

Posted: 2022-05-22 Expires: 2022-06-22

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SOC Timing Lead

Intel
Folsom, CA 95630

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