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Job CodeJR0211327
As an SoC Timing Lead,
you will be part of the design team working on the next generation
Xeon server product SOCs. This will be a fast-paced dynamic
environment where you will lead a high performance design team
towards full convergence of timing across the entire
SoC.
You will define project timing goals along
with architects and other project planners, and you will work
closely with the physical design manager and across the entire
physical design team to execute those goals and converge
timing.
You will guide the timing team in work
with silicon architects, RTL design engineers, internal/external IP
vendors, PESG, Synopsys and other EDA vendors, the DFT/DFD teams
and others to converge the design.
You will be
part of the Xeon SoC product design team that encourages
innovation, learning, team collaboration and thinking outside of
the box to address product development
challenges.
This role requires strong
partnership between the overall physical design manager, the timing
team manager, partition managers and technical leads to drive
execution.
Expectations include
developing and defining methodologies to ensure the highest
possible Silicon quality, overseeing the development of a system of
timing indicators that enables the physical team to operate
efficiently, and ensuring high-quality timing
models.
Expert level knowledge of Primetime and
associated timing model build flows is
required.
Strong communicated skills, deep
knowledge of the physical design project life cycle and a strong
commitment to planning and executing to the project's high-level
schedule are a
must.
Qualifications
You
must possess the below minimum qualifications to be initially
considered for this position. Preferred qualifications are in
addition to the minimum requirements and are considered a plus
factor in identifying top candidates.
Minimum Qualifications:
The candidate
must have a Bachelor's degree in Computer or Electrical
Engineering with 9+ years of industry experience -OR- a
Master's degree in Computer or Electrical Engineering with
6+ years of industry experience with:
Timing analysis using Primetime tools, hierarchical timing
build flows such as timing prep, and timing bucketizaton flows such
as Timing Lite.
Preferred Qualifications:
Experience serving as Technical leader of SOC/ASIC
designs responsible for timing convergence, planning, and execution
from TR to TI.
Proven track record of strong partnership
and collaboration with managers, technical leads, the RTL design
teams PESG and other project
stakeholders.
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
Other
Locations
US, California,
Folsom;US, California, Santa Clara;US, Massachusetts, Hudson;US,
Oregon, Hillsboro;US, Texas,
Austin
Intel
strongly encourages employees to be vaccinated against COVID-19.
Intel aligns to federal, state, and local laws and as a contractor
to the U.S. Government is subject to government mandates that may
be issued. Intel policies for COVID-19 including guidance about
testing and vaccination are subject to change over
time.
Posting
Statement
All qualified
applicants will receive consideration for employment without regard
to race, color, religion, religious creed, sex, national origin,
ancestry, age, physical or mental disability, medical condition,
genetic information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or
ordinance.
Position
of Trust
This role is a Position
of Trust. Should you accept this position, you must consent to and
pass an extended Background Investigation, which includes (subject
to country law), extended education, SEC sanctions, and additional
criminal and civil checks. For internals, this investigation may or
may not be completed prior to starting the position. For additional
questions, please contact your
Recruiter....
Annual Salary Range for jobs which
could be performed in US,
Colorado:
$171,710.00-$274,890.00
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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