26 days old

SoC Timing (STA) Lead

Intel
Folsom, CA 95630
  • Job Code
    JR0226771
Job Description

Are you passionate about technology? Thrive in a diverse environment? If so, then the Xe Silicon Engineering Team has an excellent opportunity for you. XSE is responsible for delivering industry-leading GPU (3D, media, compute, and display) hardware, intellectual property (IP) blocks and system-on-a-chip (SoC) products for Client discrete graphics and data center high performance computing. We strive to lead the industry through continuous innovation and world-class engineering.

We are looking for an experienced SoC Timing (STA) Lead to join the team. You be will be part of our XIS IP Physical Design team that defines and delivers high performance SoC solutions to client and server markets. The team is responsible for all SoC level physical design optimization and verification ranging from Floorplanning, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN aspects, Layout Verification etc.

In this position you will help us with the following responsibilities:

  • You will be part of a team implementing Discrete and Integrated Graphics SoCs on leading edge process technologies.
  • The ideal candidate will be responsible end to end ownership of Timing (STA) for a given SoC.  
  • Responsibilities will include all aspects of Static Timing Analysis including clock definition, timing constraints, repeater planning, hierarchical timing aspects, 3DIC timing modeling, guardbands, variation modeling and more.
  • The candidate is also expected to involve in product definition aspects such as defining Voltage-Freqency (VF) curves understanding the product/performance requirements, reliability requirements, etc.
  • Responsibilities will include showcasing technical leadership and driving through other junior members of the team.
  • The candidate would be required to work closely with a large team to converge timing, resolve issues which arise during the design cycle and take the key learnings into the next product cycle.
  • Good interpersonal/communication skills are necessary due to the nature of work, size/complexity of products and the size of the team.

Behavior traits that we are looking for:

  • Strong communication and inter-personal skills.
  • Ability to work independently
  • Proactive drive to achieve high-quality results through strong team-work


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job.

Minimum Qualifications

Must have a Bachelor's degree in Electrical/Electronics, Computer Engineering, Computer Science or related field with 6+ years of relevant experience or a Master's degree in the same fields with 4+ years of experience.

Your experience should be in the following areas:

  • Experience in ASIC SoC Physical Design
  • Experience as Timing (STA) Lead in an SoC type programs
  • Deep expertise in industry standard EDA tools
  • Understanding of leading edge methodologies in the Static Timing Analysis and related domains
  • Understanding of product performance aspects such as Workloads, Reliability, Yield

Preferred Qualfications:

  • Knowledge of SoC integration aspects such as floorplan, RTL2GDS, verification aspects of ASIC design blocks
  • Hands-on experience hardening (RTL to GDS) blocks in leading technologies
  • Knowledge and Experience with Unix/ Linux, Perl and TCL

Inside this Business Group

The focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center.  Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-09 Expires: 2022-07-10

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SoC Timing (STA) Lead

Intel
Folsom, CA 95630

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