23 days old

Sr. Director, ASIC Design

Intel
San Jose, CA 95113
  • Job Code
    JR0219857
Job Description

  • The Programmable Solutions Group (PSG) is building leading edge FPGA products that incorporate the best-in-class programmable fabric, transceivers, DDR IO, embedded memories, and DSP capabilities, all at the leading edge process nodes with 2.5D and 3D integration at package level. The FPGA product family includes several forward-looking, market-specific products with a combination of hardened and programmable IP to enable the best system performance and power. We are looking for a leader who can help define and drive high-performance IP and subsystems that enable advanced protocols on Ethernet, PCIe, CXL, and accelerator blocks tuned to specific market needs. The team consists of highly talented Directors, managers, micro-architects, and engineers with domain expertise and proven track records. In this role, you will be responsible for building and managing the IP and subsystem development across a portfolio of products at multiple process nodes. You will drive advanced methodologies with intent to drive higher levels of productivity and achieving high quality in the areas of performance, power, area, timing convergence, DFT, debug, and pre- and post-silicon validation. You will also drive resource planning for the global team to optimize resource usage and balance the needs of all projects. You will be reporting to the leader of product design in CFE (Custom FPGA Engineering) within the Programmable Solutions Engineering in PSG. The design team is responsible for design, integration, productization, and project management for all FPGA silicon products.

Additional Skills

Track record of bringing innovation to product development.
Skills to scale from fine details of design to big picture view of product goals.
Excellent written and verbal communication skills


Qualifications

Minimum Qualifications

BS  in Computer Science or Electrical Engineering or related field with 12+ years of relevant experience 

8+ years of experience driving multiple silicon products in the areas of design and methodologies.

8+ years of experience in ASIC design for transceivers or DDR IO, embedded memories

5+ years of experience leading a large and world-wide teams

 

Preferred Qualifications

5+ years of experience delivering complex subsystems at leading edge process nodes

5+ years of experience in validation, debugging (pre and post silicon validation)

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Santa Clara


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-02 Expires: 2022-06-02

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Sr. Director, ASIC Design

Intel
San Jose, CA 95113

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