7 days old

Sr Member of Technical staff- SOC Design Engineer

San Jose, CA 95113
  • Job Code
Job Description

We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.As a member of Intel's Programmable Solutions Group (PSG), you will use your knowledge of Logic Design, Verification, and FPGA technology to lead pre-silicon verification efforts (including IP, integration, and full-chip aspects), both internal and external, to use the Structured ASIC technology. The position requires a self-driven candidate with deep knowledge in design, verification, and communication interfaces, coupled with good communication skills.

Structured ASIC team: This is a structured ASIC team under Intel's PSG targeting 5G, cloud computing, and high-end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC. Learn more about us: https://www.anandtech.com/show/16266/intels-new-easic-n5x-series-hardened-security-for-5g-and-ai-through-structured-asics https://www.intel.com/content/www/us/en/products/programmable/fpga-vs-structured-asic.htm https://www.intel.com/content/www/us/en/design/products-and-solutions/structured-asics/overview.html??

Areas of responsibility for this role include, but not limited to the following:

  • Own verification of IP integration and/or SoC level flows
  • Be the go-to expert on the overall architecture, implementation of complex features/flows/protocols, and their interactions with rest of the SoC and with the platform
  • Develop verification strategy, requirements, environments, tools, and methodologies
  • Apply your knowledge of verification principles and techniques and your judgement to write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
  • Run tests, debug failures to root cause, and recommend solutions
  • Collaborate with cross-functional folks to drive continuous improvement to both the design, to verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably


Bachelors' degree in Electrical Engineering, Electrical Electronics or Computer Engineering.

Minimum Qualifications
7+ years of experience in Pre-Si verification of ASICs, including high speed IO and SERDES.
7+ years of experience in FPGAs or ASICs, SERDES, and networking applications.
7+ years of experience in test plan definition and testcase development in C/Assembly/System Verilog.
7+ years of experience in verifying design at RTL level and gate-level simulation.
7+ years of experience in coverage analysis, performance verification, and use-case verification.
4+ years of experience in functional test vector development and post silicon bring-up/debug.
3+ years of experience with scripting languages (e.g., Perl, Python, Shell).

Preferred Qualifications
Experience in analog and digital design.
Masters' degree in Electrical Engineering, Electrical Electronics or Computer Engineering with 7+ years of experience.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-18 Expires: 2022-06-18

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Sr Member of Technical staff- SOC Design Engineer

San Jose, CA 95113

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