7 days old

Sr. Pre-Silicon Verification Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0208422
Job Description

The IP Engineering Group (IPG) organization is responsible for developing leadership IPs that power-winning products for our customers and Intel. IPG develops a broad portfolio of IP, including standard cell libraries, memory compilers, network on chip, audio and sensing IP, analog IP, and both controllers and PHYs for serial and parallel IO IP such as DDR/LPDDR, PCIe, USB, and Serdes.

The Customer Engineering Group (CEG) within IPG will be a dynamic and versatile team of engineers who directly engage with both the IP design teams and internal/external customers in all phases of IP development (architecture, pre-silicon, post silicon execution, validation, and debug).

CEG engineers will embody customer obsession by quickly resolving customer issues and providing hands on debug on a wide range of technical issues spanning all design domains (logic design, timing, physical integration, emulation, documentation, and customer training).

Responsibilities for this candidate can include but are not limited to the following:

  • Engage in the upfront identification and documentation of customer requirements, working with the IP design teams to disposition requests.

  • Proactively engage customers to avoid issues by anticipating roadblocks and working with the customer and IP design team to take preventative action.

  • Provide clear and direct answers to customer questions.

  • Also work with IP design teams to ensure high quality documentation is available.

  • Investigate, debug and disposition customer bugs/sightings in a responsive and timely manner.

  • Drive resolution of customer issues related to the IP collaterals generation, logic design verification, IP release, and integration in SOC environment.

  • This may involve travel to customer sites.

  • Prepare customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug.


Qualifications

  • BSEE or MSEE, with experience in ASIC and SoC development
  • 10+ years of experience in Module and Chip Level Design Verification process
  • 3+ years of experience in UVM Testbench plan and development from scratch.
  • 3+ years of experience in Pre-silicon verification experience with system Verilog, C and VHDL, and advanced Verification environments and components
  • Enjoy debugging, and problem solving in a team environment
  • 2+ years of experience with at least one or more industry standard IO interfaces including DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc. Either PHY or Controller experience is good.

Desired Qualifications:

  • 3+ years of any of the following: Experience with Digital design data protocols like DDR, DPHY/MIPI, JESD, AMBA, USB, I2S, and PCIe.
  • Experience integrating into large SOC systems with embedded processor cores (x86, ARM, ARC, or similar).
  • Experience working with low power design, boot-up/Firmware sequencing, power-cycling, HW/FW interaction validation.
  • Low Power Verification, UPF integration/simulation, Multipower domain isolation/integration experience
  • Able to work independently with design team and customers to solve issues either remotely or onsite.  

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Folsom;US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-18 Expires: 2022-06-19

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Sr. Pre-Silicon Verification Engineer

Intel
Santa Clara, CA 95050

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