12 days old

SRAM Design Engineer

Hillsboro, OR 97123
  • Job Code
Job Description

You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel's advanced CMOS process technologies.

In this position your responsibilities will include, but may not be limited to:

  • Memory pathfinding activities and power, performance, area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
  • Memory bit-cell and complex periphery IC layout and automation.
  • Memory array/IP design, memory circuit innovation, test-chip design.
  • Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.

The Advanced Design (AD) team is part of Intel's larger Design Enablement (DE) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DE is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.


You must possess the "minimum qualifications" listed below to interview for this position. "Preferred qualifications" are not required but may work to your advantage during the interview process.

Minimum Qualifications

  • Ph.D. in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 3 years of professional experience gained through either internships or full-time employment.


  • Master's degree in one of the same fields listed above, including 6 years of professional experience gained through either internships or full-time employment.

Technical Experience must be in the following areas:

  • CMOS ASIC design flow
  • Custom digital circuit design, simulation, layout design, and verification
  • EDA tools used for analog, digital and mixed-signal circuit design
  • Post-Si validation

Preferred Qualifications:

  • Design, characterization, and verification of custom memory circuits such as SRAM, Register Files, ROM, DRAM, MRAM, etc.
  • Design trade-offs between power, performance, and area (PPA)
  • Design technology co-optimization (DTCO)

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-09 Expires: 2022-06-09

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SRAM Design Engineer

Hillsboro, OR 97123

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