2 days old

Staff DFT (Design for Test) Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0217935
Job Description

Develops and supports design for test (DFT) structures. Determines design for test approaches and develops DFT architecture. Designs and verifies DFT structures for memories (MBIST), digital and analog circuitry. Performs scan synthesis. Creates, simulates and verifies automatic generated test patterns (ATPG). Creates functional tests and corresponding test patterns. Knows about failure mechanisms in silicon production and creates test algorithms. Supports silicon bring up of test patterns. Performs diagnosis of test patterns on silicon and optimizes test time.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. This Position is not eligible for Intel immigration sponsorship


Minimum Qualifications:

Bachelor's Degree in Electrical engineering or related STEM degree with 6+ years of experience in DFT ( Design for Test) on products that went into production

Master's degree with 4+ years of experience in DFT on products that went into production.

6+ years of relevant experience in 2 or more of the following:

1) Vendor tools such as: scan ATPG, memory BIST, industry DFT practices in HSIO test, PLL test

2) Debug methods and production test equipment.

3) Writing scripts and small software programs for automation

4) Using RTL and physical design tools,

Preferred qualification:

Experience in Foundry Technology and Packaging Technology.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.



Other Locations

US, Arizona, Phoenix;US, California, Folsom


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-21 Expires: 2022-06-21

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Staff DFT (Design for Test) Engineer

Intel
Santa Clara, CA 95050

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