19 days old

Staff - SoC Design and IP Engineer

Santa Clara, CA 95050
  • Job Code
Job Description

At Intel, the IP Engineering Group (IPG) organization is responsible for developing leadership IPs that power-winning products for our customers and Intel. IPG develops a broad portfolio of IP, including standard cell libraries, memory compilers, network on chip, audio and sensing IP, analog IP, and both controllers and PHYs for serial and parallel IO IP such as DDR/LPDDR, PCIe, USB, and Serdes.

The Customer Engineering Group (CEG) within IPG will be a dynamic and versatile team of engineers who directly engage with both the IP design teams and internal/external customers in all phases of IP development (architecture, pre-silicon, post silicon execution, validation, and debug). CEG engineers will embody customer driven by quickly resolving customer issues and providing hands on debug on a wide range of technical issues spanning all design domains (logic design, timing, physical integration, emulation, documentation, and customer training).

Your specific responsibilities may include but are not limited to the following:

  • Work with cross-functional teams to develop SoC and IP Integration into SoC.

  • Engage with IP development team to ensure all IP collaterals are generated and provided.

  • Fully own assigned IPs and work with Internal and external customer and help them integrate Intel IPs to SoC and provide technical support.

  • Drive resolution of customer issues related to the IP collaterals generation, logic design verification, IP release, and integration in SoC environment. This may involve travel to customer sites.

  • Engage in the upfront identification and documentation of customer requirements, working with the IP design teams to disposition requests.

  • Prepare customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • BSEE or MSEE, with experience in ASIC and SoC development
  • 10+ years of experience in RTL design using Verilog/System Verilog
  • 7+ years of experience with VCS, Verdi, Spyglass or equivalent tools
  • 5+ years of experience in SOC architecture and chip level/subsystem integration
  • 3+ years of experience in partitioning, synthesis, floorplan, IO designs, clock tree and timing closure for ASICs.
  • Enjoy debugging, and problem solving in a team environment
  • Minimum 3 years of experience with at least one or more industry standard IO interfaces including DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc. Either PHY or Controller experience is good.

Preferred Qualifications:

  • Good understanding of industry standard IO specifications
  • 3+ years of experience with IP development experience is strong plus.
  • Proficient in scripting languages like Perl/Tcl/Python and power-aware RTL and UPF flow is a plus.
  • Experience with digital flow for RTL2GDS development.
  • Able to work independently with design team and customers to solve issues either remotely or onsite.  
  • 3+ years of experience with ASIC synthesis flows and working with physical design team is a plus
  • Good understanding of IP integration and design flow challenges within the context of subsystems and SOCs.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Folsom;US, Oregon, Hillsboro

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-13 Expires: 2022-07-14

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Staff - SoC Design and IP Engineer

Santa Clara, CA 95050

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