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Standard Cell Library Pathfinding and DTCO Lead
-
Job CodeJR0210752
Advanced Design Group
under Design Enablement in Technology Development has primary focus
of Design-Technology Co-optimization (DTCO) and Foundational IP
development to support both the Technology Development organization
and Intel's IP/Product design teams. Advanced power, performance
and area (PPA) analyses are conducted across domains to guide
Technology Development's research, pathfinding and technology
definition.
Library Technology Group in Advanced
Design is looking for a highly motivated and experienced individual
to lead the pathfinding, development and optimization of standard
cell libraries to enable best-in-class IP and product design on all
generations of Intel
technology.
As a technical lead of library pathfinding team, you are responsible for:
- Leading the standard cell pathfinding activities (cell layout architecture and modeling) with active collaboration with process technologists, product design stake holders, and EDA vendors to achieve best-in-class cell/block level PPA and competitive EoU (Ease of Use) through DTCO.
- Leading the standard cell benchmarking and competitive analysis activities and driving technology enhancements for FIP (foundation IP) leadership.
- Supporting test-chip planning and Si validation of standard cells to track yield, Vmin and power/performance.
Preferred Requirements:
- 10 years of experience in foundational IP pathfinding in DTCO, silicon implementation, or technology development
- Successful experience in leading std cell library pathfinding and definition to optimize PPA through DTCO on advanced technology nodes strongly preferred
- In-depth knowledge in digital design including CMOS combinatorial logic and sequential circuit and layout, and familiarity with design tradeoffs as well as standard cell modeling, extraction and characterization highly desired
- Experience in EDA tool/flow/methodology, product and IP developments
- Familiar with foundry ecosystem and benchmarking practice
- Excellent communication and interpersonal skills to champion initiatives internally and externally, and for effective communication with executive management and external partners
- Technical, analytical and cross-functional collaboration skills
Qualifications
- MS or Ph.D. in Electrical Engineering, Computer Science, Computer Engineering or other related field of study
- Minimum of 10 years of experience in process development or product design in the semiconductor industry
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth.
Other
Locations
US, California, Santa
Clara
Intel
strongly encourages employees to be vaccinated against COVID-19.
Intel aligns to federal, state, and local laws and as a contractor
to the U.S. Government is subject to government mandates that may
be issued. Intel policies for COVID-19 including guidance about
testing and vaccination are subject to change over
time.
Posting
Statement
All qualified
applicants will receive consideration for employment without regard
to race, color, religion, religious creed, sex, national origin,
ancestry, age, physical or mental disability, medical condition,
genetic information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or
ordinance.
Position
of Trust
This role is a Position
of Trust. Should you accept this position, you must consent to and
pass an extended Background Investigation, which includes (subject
to country law), extended education, SEC sanctions, and additional
criminal and civil checks. For internals, this investigation may or
may not be completed prior to starting the position. For additional
questions, please contact your
Recruiter....
Work Model
for this Role
This role will be
eligible for our hybrid work model which allows employees to split
their time between working on-site at their assigned Intel site and
off-site.
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