14 days old

Structural Design Engineer for Test Chip Development

Intel
Phoenix, AZ 85003
  • Job Code
    JR0222502
Job Description

The world is transforming - and so is Intel!  Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives.

Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful!

In this position, you will be part of the Testchip team in IPG - E2G (Emerging Technologies Engineering Group). This team develops testchips to validate IP for future Intel products. The testchip team works on internal leading edge process technology test chips and also works on external process technology testchips.

Responsibilities will include but not limited to:

  • Perform and analyze APR results at the partition level or fullchip level through tape-in.

  • Conduct floor planning activities including trade-offs in Macro placements, Power Grid definition, and integration requirements.

  • Perform DRC and LVS layout verification activities.

  • Conduct Power/Performance/Area trade-offs with respect to design optimization.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 7+ years of experience.

OR

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years of experience with:

  • Synopsys or Cadence design (RTL to GDS) tools.

  • Synopsys-Primetime.

  • ICV or Calibre DRC/LVS Layout cleanup.

  • FEV/LEC verification.


Preferred Qualifications:

  • Experience with RTL/Logic design Verilog, VCS, etc.

  • Solid analytical willingness, problem solving and communication skills.

  • Willing to work independently and at various levels of abstraction.

  • Experience in Perl, TCL/Tk programming.

  • Experience with TFM (Tools, Flows, Methodology) Development

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Posted: 2022-06-22 Expires: 2022-07-23

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Structural Design Engineer for Test Chip Development

Intel
Phoenix, AZ 85003

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