20 days old

Structural Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0221281
Job Description

As an IP Structural Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets.

We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization. You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing.

Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to:

  • Oversees definition, design, verification, and documentation for SoC (System on a Chip) development.

  • Block-level floor planning, interconnect planning and UPF based power delivery methodology.

  • Logic synthesis of design blocks using Synopsys Design Compiler DCT- Formal Equivalence Verification FEV using Cadence's Conformal tool.

  • Auto Place-and-Route APR using Synopsys Fusion Compiler tools.

  • Timing and power verification using Synopsys PrimeTime as well as Intel tools.

  • Layout Verification and DRC analysis.

What we offer:  

  • We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth.  

  • As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results.  

  • We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation).  

  • We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work!  

  • We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today. 


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and internship experience. 

Minimum Qualifications:
Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of experience.

OR

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience.

OR

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 1+ years of experience in:

  • CMOS circuit design, and layout verification.

  • Industry standard CAD tools/flows for digital and/or analog design.


Preferred Qualifications:

Experience in:

  • Fusion Compiler/Primetime Process and Design co-optimization for Density/Performance improvements RTL based power estimation and optimization.

  • Experience in CPU/ASIC design methodology and flow development, particularly in the RLS, Structural Design, APR and low power optimization domains.

  • Unix skills, programming skills in TCL, Perl Script and shell scripting.

  • Good understanding of overall CPU/SOC design cycle and requirements.

  • Willing to multi-task and flexibility to work in a global environment.

  • Good communication skills and have self-motivation.

  • Good analytical and Problem solving skills.

  • Experience in working on high frequency designs and methodologies.

  • Experience in leading small teams to design IPs.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.



Other Locations

US, Colorado, Fort Collins;US, Oregon, Hillsboro


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$132,940.00-$199,800.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-06-08 Expires: 2022-07-09

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Structural Design Engineer

Intel
Santa Clara, CA 95050

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