Job Description
As a Structural Design Partition Lead, you will be part of the design team working on the next generation Xeon server product SOCs. This will be a fast-paced dynamic environment where you will work in high performance design team focused on a wide spectrum of structural design and backend physical design activities. Your role will be to plan and lead SoC or IP partition development from RTL to TI-ready GDS. You will work closely with silicon architects, RTL design engineers, internal/external IP vendors, and DFT/DFD teams, getting exposure to all aspects of product development. You will be part of the Xeon SoC product design team that encourages innovation, learning, team collaboration and thinking outside of the box to address all of our product development challenges. This role requires strong partnership between Tech Lead and Manager to drive execution through deep technical understanding and ability to highlight critical challenges. You will also be responsible for working with and leading a team of more junior partition owners executing partitions within the same cluster. Responsibilities include synthesis, place, clock and route; timing closure, FEV and full layout closure. You will be involved in methodology definition tasks as well as executing to project schedules. Good knowledge of process, Fusion Compiler, ICC2, and Prime Time are required.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. MINIMUM QUALIFICATIONSThe candidate must have a Bachelor's degree in Computer or Electrical Engineering with 9+ years of industry experience -OR- a Masters degree in Computer or Electrical Engineering with 6+ years of industry experience and expertise in synthesis, place and route static timing analysis using Primetime tools, DFT flows, and low power design PREFERRED QUALIFICATIONS Experience as technical leader of SOC/ASIC designs responsible for physical convergence, planning, and execution from synthesis to GDS. Proven track record of strong partnership and collaboration with managers, RTL design and other partner teams. In addition to the qualifications listed below, the ideal candidate will also have strong written and verbal communication skills and the ability to drive a small team.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$132,940.00-$199,800.00

Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.