4 days old

Structural Test Plus Design Architect

Intel
Hillsboro, OR 97123
  • Job Code
    JR0208691
Job Description

Join Intel and engineer the future.


Join Intel during an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So, join us and help us create the next generation of technologies that will shape the future for decades to come.

Take Intel Structural Test Plus (STP) to the next level. STP is a designed set of test cards (CPU, DDR5, PCIe) that allows for server baseboards to be electrically tested in validation and volume manufacturing. As an STP Architect you will be driving STP designs (HW, Firmware and SW) and test strategies for next generation XEON server products and be a key member of the Data Platforms Engineering Operations (DEO) team within the Data Platforms Engineering and Architecture (DPEA) group supporting server platform development. DPEA invents, designs, and builds the world's most critical computing platforms and in this position the STP Architect will work in parallel with product architects and designers to drive shift left testing of new reference designs. This position will support reference platform development by providing high confidence in board connectivity of the high-speed busses and manufacturing defect free baseboards in these areas.

Position Description:
In this position, you will be driving early engagement with our server engineering and architecture teams to explore, invent, design, enable, and deliver new test hardware, firmware and software for next generation reference designs and systems. You will provide vital support to develop these test solutions and drive the implementation and execution during the new product development of server products by direct involvement and coordination with Intel's outsource manufacturers, internal and external design teams.

Your responsibilities will include, but not be limited to:

  • Drive new STP test card designs utilizing FPGA to intercept new Platform Architecture and Reference Platform boards.
  • Coordinate with CAD teams for layout of STP designs.
  • Coordinate with mechanical teams to enable spacer designs for pre-power on and power on heat sink compatibility.
  • Drive PCB, PCBA and spacers procurement of STP test cards.
  • Invent and Develop New Test Technologies to continuously increase STP test coverage for next generation server platforms.
  • Drive validation of new STP hardware, create test procedures, train ODMs/CMs for factory deployment.
  • Continuous improvement of the STP SW GUI and automated test generation tool.
  • Drive Strategic Collaborative Engineering Engagements with our partner groups and divisions.


Qualifications

Minimum Qualifications:

  • Candidate must possess a Bachelor of Science degree (with 10+ years of experience) or Masters of Science degree (with 5+ years of experience) or PhD degree (with 3+ years of experience) in Electrical Engineering, Computer Science, Industrial Engineering, Mechanical Engineering or a related engineering field.


Preferred Qualifications:

  • Experience with Cadence Allegro Design Entry HDL to generate new schematic designs.
  • Experience with Cadence PCB designer.
  • Experience with Python programming.
  • Experience with Quartus Prime Software for Altera FPGA development.
  • Working knowledge or experience in Printed Board Assembly (PBA) and test flow through the factory.
  • Strong technical design review skill.
  • Working knowledge of Design for Testability (DFT), throughput analysis, quality control systems, and cost/benefit analysis.
  • Prior experience driving issue resolution between manufacturing sites and product development teams.
  • Willing to work well in a diverse team environment.
  • Willing to make technical decisions and provide technical direction.
  • Excellent written and verbal communication skills.
  • Strong team building skill.

Inside this Business Group

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-15 Expires: 2022-06-15

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Structural Test Plus Design Architect

Intel
Hillsboro, OR 97123

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