18 days old

System Modeling Engineer for HSIO IPs

Santa Clara, CA 95050
  • Job Code
Job Description

You will be part of the Mixed Signal IP Development team chartered to deliver High-Speed Serial I/O (HSIO) IP for state of the art, next generation High-Speed Serdes.

Design responsibilities may consist of but are not limited to:

  • Build system modeling for circuit blocks, including TX (Transmitter), CTLE (continuous time linear equalizer), DFE (decision feedback equalizer), DCO (digital controlled oscillator) and Digital Signal Processing blocks in Matlab Simulink.
  • Collaborate with other design disciplines contributing to the creation of behavioral modeling, to mixed signal validation, and to the creation of IBIS-AMI libraries.
  • Drive block level specification and circuit microarchitecture definition based on system link margin analysis.
  • Interact with internal and external stakeholders to evaluate system performance in various package and platform channels.



You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience - OR - Master's Degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of experience.

  • Experience with High-Speed mixed signal circuit design
  • Experience with circuit modeling in deep sub-micron process.
  • Proficiency in Matlab and Simulink.
  • Understanding of statistical analysis, jitter analysis, digital signal processing, and signal integrity.
  • Knowledge of filter design and basic control theory.
  • Strong verbal and written communication skills as well as a can-do attitude.
  • Excellent analytical and problem-solving skills.
  • Excellent collaboration skills to work with peer teams.

Preferred Qualifications:

  • Proficiency in C/C++ and hands-on experience of gcc and Microsoft Visual Studio.
  • Knowledge of High-Speed Serdes Protocols (PCIe, UPI, USB, Ethernet), IBIS-AMI specification, and Keysight ADS is a plus.
  • Hands-on experience of Cadence Schematics Design Environment and Synopsys Verdi tools.
  • Hands-on experience with revision control software (git, svn)

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, Colorado, Fort Collins

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here
Posted: 2022-05-01 Expires: 2022-06-01

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System Modeling Engineer for HSIO IPs

Santa Clara, CA 95050

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