24 days old

Technical Lead Applications Engineering Manager

San Jose, CA 95113
  • Job Code
Job Description

Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person globally, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenges that come with changing the world.

We are a global leader, creating world-changing technology that enables progress and enriches lives. Intel is at the intersection of several technology inflections - artificial intelligence, 5G network transformation, and the rise of the intelligent edge- that together will shape the future of technology.  As a member of Intel's Programmable Solutions Group, you will use your knowledge of Logic Design, Verification, and high speed IO/SERDES technology to lead efforts at a system level in enabling customers, both internal and external, to use the Structured ASIC technology.

The position requires a self-driven candidate with deep knowledge in design, verification, and communication interfaces, along with excellent communication skills. Structured ASIC team: This is a structured ASIC team under Intel's PSG and is targeting 5G, cloud computing, and high end consumer application space. Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs bridging the gap between FPGA and Custom ASIC. 


Responsibilities include but not limited to:

  • Provide applications leadership to internal and external customer programs pre and post silicon

  • Manage/Develop collaterals such as Handbook, Datasheet, and Application notes

  • Create protocol specific use models. Perform protocol specific characterization and author characterization reports

  • Work with IP teams and customers to ensure proper usage of the SERDES for various applications and protocols

  • Define methodology for high speed serial IO measurements

  • Validate PCS and PMA blocks of the transceiver Leading and dotted line managing the characterization team

  • Engage customers to explain current and future SERDES architectures and requirements

  • Gather requirements for next generation SERDES and demonstrating technology capability

  • Lead the advanced customer support and design win effort as it relates to SERDES Design, Simulation, Bring Up Characterization, and Evaluation Train and provide engineering support to Intel's worldwide customers and Applications team



Minimum Education Requirements:

  • Bachelors' degree in Electrical Engineering, Electrical Electronics, or Computer Engineering

  • Masters' degree in Electrical Engineering, Electrical Electronics, or Computer Engineering

Minimum Qualifications:

  • Seven plus years of experience in design, development, implementation of FPGAs or ASICs, SERDES

  • Five plus years of SERDES and protocols, such as PCI Express, or 10GBASE-KR/SR/MR/ER/LR, 25GBASE-KR, or JESD 204X, or CPRI/OBSAI, or DisplayPort or HDMI or VbyOne

  • Five plus years of experience in programming and data analysis with either Python, Matlab, Perl, C++ or any Object-Oriented language

  • Five plus years of experience in SI Concepts, including sources and causes of noise and jitter

  • Two plus years of experience in testing equipment, such as high-speed oscilloscopes BERTs and VNA

Preferred Qualifications:

  • 2+ years of experience in communication systems theory relating to SERDES

  • 2+ years of experience in SERDES IP architecture and implementation

  • Experience in analog and digital design

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, California, San Diego;US, California, Santa Clara;US, Texas, Austin

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-05-01 Expires: 2022-06-01

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Technical Lead Applications Engineering Manager

San Jose, CA 95113

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