The Xeon Engineering Group (XEG) Emulation CoE is looking for a senior or principal engineer with emulation, SoC validation, and design methodology experience to join our organization. This individual will be responsible for driving innovations across all areas of CoE operation and beyond to increase design and validation velocity, improve validation effectiveness, and improve Xeon product quality. The Emulation CoE has responsibility across all Xeon products for emulation model build and bringup, validation capability improvements, IP and feature enabling, emulation SW tools including multiple test generators, and select areas of SoC validation.

The successful candidate will need to effectively interface with and influence managers, architects, pre-Si validation teams, RTL designers, and FW and SW teams across multiple organizations to understand major problems, propose solutions, and drive change across Xeon design and validation processes. The goal will be to improve the quality of design and validation collateral upstream of emulation, improve emulation processes and capabilities, and ultimately deliver emulation models more quickly, with higher initial design quality, and with greater capabilities to find deep, silicon-quality bugs. The candidate should have a proven track record of delivering exceptional results through hands-on technical involvement and cross-team collaboration.

Professional Traits:
Exceptional technical leadership skills and expertise in solving complex problems through technical TFs to deliver SoCs and products at a pace faster than prior art.
Ability to contribute in technical design and validation reviews and to create and present critical program and technical assessments to senior management.
Aptitude and desire to mentor other technical leads within the organization.
Proven track record of product development from concept through production.
Solid track record of collaboration and building partnerships to get results cross-organization and cross-geo.

Qualifications

The applicant should have a BS, MS or PhD in Electrical/Computer Engineering, Computer Science or a related field with 15 years of technical experience in SoC design and/or validation/verification.

� Experience using hardware emulation to validate SoC designs, preferably with experience building and enabling emulation models.
� Experience with SoC design methodologies and processes.
� Extensive experience with pre-Si SoC validation methodologies, tradeoffs, and challenges, including multiple programs driven from Path Finding through Production.
� Experience integrating and validating RTL with FW, including BIOS.
� Mindset of continuous improvement with a track record of removing inefficiencies and improving processes across design and/or validation to improve velocity and quality.
� Knowledge of C/C++, System Verilog, and scripting languages.

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, California, Santa Clara

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Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.