1+ months

Xeon SoC Pre-Si Validation Lead

Intel
Santa Clara, CA 95050
  • Job Code
    JR0227228
Job Description
Xeon Engineering Group - XEG leadership team is looking for a Senior Technical leader/Architect in Validation with prior SoC or IP pre-silicon Validation experience to join our organization. This individual will be responsible for driving overall product quality of Xeon server program(s) through validation strategy, test plans content development and content execution, improving coverage, working with other managers and tech leads within XEG and other partner organizations. This candidate would be expected to effectively interface and influence architects, microarchitects, pre-silicon simulation teams, emulation teams and post-si validation partner teams to define/develop/execute cohesive validation plans to get to high quality Tape-In and PRQ. We also expect this candidate to define new and innovative strategies to shift-left and find HW/FW bugs faster and prior to Tape-In, minimizing any escapes into post-si. The candidate should have a proven track record of delivering exceptional results through hands-on technical involvement either through content development or debug or writing validation strategies. Expertise in validating complex IPs, experience in creating verification environment from scratch for IP/Subsystem/SoC Pre-si Verification with knowledge of system Verilog and verification methodologies like UVM, OVM, sound understanding of functional test strategies, debug flows, system validation strategy is a strong requirement.Professional Traits:Exceptional technical leadership skills and technical expertise in solving complex problems through technical TFs and help deliver SoCs and products at a pace faster than prior art. Senior individual who can contribute in the technical reviews of design and mentor other technical leads in the organization and own critical program and technical assessment to senior management. Solid track record of collaboration and building and strengthening partnership willing to work effectively and influence leads or teams across organizations. Proven track record of product development from concept all the way through to production, expertise in Silicon Product development and Verification/Validation for complex SoCs. Expertise in validating complex IPs, experience in creating verification environment from scratch for IP/Subsystem/SoC Pre-si Verification with knowledge of system Verilog and verification methodologies like UVM, OVM, sound understanding of functional test strategies, debug flows, system validation strategy is a strong requirement. Experience in silicon bring up, debug in the lab will be a plus.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and internship experience.Minimum Requirements:Candidate should have a BS in Electrical or Computer Engineering Science or related field with 8+ years of technical experience-OR-MS in Electrical or Computer Engineering Science or related field with 6+ years of technical experience-OR-PhD in Electrical or Computer Engineering Science or related field with 4+ years of technical experienceRelated technical experience should be in/with:Silicon Design and/or Validation/Verification.Preferred experience will include:Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.OVM/UVM, System Verilog, constrained random verification methodologies.The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.Experience in Xeon CPU Pre-Silicon or Post Silicon Validation

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posted: 2022-07-09 Expires: 2022-08-09

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Xeon SoC Pre-Si Validation Lead

Intel
Santa Clara, CA 95050

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